/**********************************************************************************
* 	Just for vertification. It is suggested that using pll to generate clk in fpga.

*   sys_clk = 50MHz
*   clk_1 = 1Hz
**********************************************************************************/

module freqDiv #(
  parameter   SYS_CLK = 50_000_000
)(
  input   wire        sys_clk,
  input   wire        rstn   ,

  // output  reg         clk    ,
  output  reg         clk_1
);

localparam  CNT_1  = SYS_CLK / 1;

reg   [24:0] cnt_1 ;

/*          cnt_1           */
always @(posedge sys_clk or negedge rstn) begin
  if (~rstn)
    cnt_1   <=  25'd0;
    /* verilator lint_off WIDTH */
  else if (cnt_1 == CNT_1 / 2 - 1)
    cnt_1   <=  25'd0;
  else
    cnt_1   <=  cnt_1  + 1'b1;
end

/*          output clk          */
always @(posedge sys_clk or negedge rstn) begin
  if (~rstn)
    clk_1   <=  1'b0;
  else if (cnt_1 == CNT_1 / 2 - 1)
    clk_1   <=  ~clk_1;
end

// always @*
//   clk = sys_clk;    // Make it resembles a pll(all clock in a system should be generated from one source).

endmodule
